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1 features ? 3.0v to 3.6v operating range advanced, high-speed, electrically-erasable programmable logic device ? superset of 22v10 ? enhanced logic flexibility ? architecturally compatible with atv750b and atv750 software and hardware d- or t-type flip-flop product term or direct input pin clocking 15 ns maximum pin-to-pin delay with 3v operation highest density programmable logic available in 24-pin package ? advanced electrically-erasable technology ? reprogrammable ? 100% tested increased logic flexibility ? 42 array inputs, 20 sum terms and 20 flip-flops enhanced output logic flexibility ? all 20 flip-flops feed back internally ? 10 flip-flops are also available as outputs programmable pin-keeper circuits dual-in-line and surface mount package in standard pinouts commercial and industrial temperature ranges 20-year data retention 2000v esd protection 1000 erase/write cycles block diagram description the atmel ?750? architecture is twice as powerful as most other 24-pin programmable logic devices. increased product terms, sum terms, flip-flops and output logic configu- rations translate into more usable gates. high-speed logic and uniform, predictable delays guarantee fast in-system performance. the atf750lvc is a high-performance programmable interconnect and combinatorial logic array logic option (up t0 20 flip-flops) output option 4to8 product terms (oe product terms) 10 i/o pins 12 input pins (clock pin) rev. 1447d?03/01 high-speed complex programmable logic device atf750lvc pin configurations pin name function clk clock in logic inputs i/o bi-directional buffers gnd ground vcc 3v supply (continued) dip/soic/tssop 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk/in in in in in in in in in in in gnd vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o in plcc 5 6 7 8 9 10 11 25 24 23 22 21 20 19 in in in gnd * in in in i/o i/o i/o gnd * i/o i/o i/o 4 3 2 1 28 27 26 12 13 14 15 16 17 18 in in gnd gnd * in i/o i/o in in clk/in vcc * vcc i/o i/o note: for plcc, pins 1, 8, 15, and 22 can be left unconnected. for superior performance, connect vcc to pin 1 and gnd to pins 8, 15, and 22.
atf750lvc 2 cmos (electrically-erasable) complex programmable logic device (cpld) that utilizes atmel?s proven electrically-eras- able technology. each of the atf750lvc?s 22 logic pins can be used as an input. ten of these can be used as inputs, outputs or bi- directional i/o pins. each flip-flop is individually config- urable as either d- or t-type. each flip-flop output is fed back into the array independently. this allows burying of all the sum terms and flip-flops. there are 171 total product terms available. there are two sum terms per output, providing added flexibility. a variable format is used to assign between four to eight product terms per sum term. much more logic can be replaced by this device than by any other 24-pin pld. with 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. product terms provide individual clocks and asynchronous resets for each flip-flop. each flip-flop may also be individu- ally configured to have direct input pin controlled clocking. each output has its own enable product term. one product term provides a common synchronous preset for all flip- flops. register preload functions are provided to simplify testing. all registers automatically reset upon power-up. absolute maximum ratings* temperature under bias.................................. -40c to +85c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc, which may under- shoot to -2.0v for pulses of less than 20 ns. maximum output pin voltage is v cc + 0.75v dc, which may overshoot to 4.6v for pulses of less than 20 ns. storage temperature ..................................... -65c to +150c voltage on any pin with respect to ground .........................................-2.0v to +4.6v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) dc and ac operating conditions 3.3v operation commercial industrial operating temperature (ambient) 0c - 70c -40c - +85c v cc power supply 3.0 - 3.6v 3.0 - = 3.6v
atf750lvc 3 clock mux output options bus-friendly pin-keeper input and i/os all input and i/o pins on the atf750lvc(l) have program- mable ?pin-keeper? circuits. if activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. this circuitry prevents unused input and i/o lines from floating to intermediate voltage levels, which cause unnec- essary power consumption and system noise. the keeper circuits eliminate the need for external pull-up resistors and eliminate their dc power consumption. enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the logic compiler device selection menu. please refer to the software compiler table for more details. once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and i/os. input diagram i/o diagram select logic to cell clock product term clk cki ckmux pin table 1. software compiler mode selection synario wincupl pin-keeper circuit atf750lvc v750c disabled atf750lvc (ppk) v750cppk enabled 100k v cc esd protection circuit input programmable option 100k v cc v cc data oe i/o programmable option
atf750lvc 4 notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. this test is performed at initial characterisation only. input test waveforms and measurement levels t r , t f < 3 ns (10% to 90%) output test load dc characteristics symbol parameter condition min typ max units i li input load current v in = -0.1v to v cc + 1v 10 a i lo output leakage current v out = -0.1v to v cc + 0.1v 10 a i cc power supply current, standby v cc = max, v in = max, outputs open c-15 com. 65 90 ma ind. 70 100 ma i os (1)(2) output short circuit current v out = 0.5v -120 ma v il input low voltage 3.0 v cc 3.6v -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.75 v v ol output low voltage v in = v ih or v il , v cc = min i ol = 16 ma com., ind. 0.5 v i ol = 12 ma mil. 0.5 v i ol = 24 ma com. 0.8 v v oh output high voltage v in = v ih or v il , v cc = min i oh = -2.0 ma 2.4 v vcc 348 ? 316 ?
atf750lvc 5 ac waveforms, product term clock (1) note: 1. timing measurement reference is 1.5v. input ac driving levels are 0.0v and 3.0v, unless otherwise specified. note: 1. see ordering information for valid part numbers. ac characteristics, product term clock (1) symbol parameter -15 units min max t pd input or feedback to non-registered output 15 ns t ea input to output enable 15 ns t er input to output disable 15 ns t co clock to output 5 12 ns t cf clock to feedback 5 9 ns t s input setup time 8 ns t sf feedback setup time 7 ns t h hold time 5 ns t p clock period 14 ns t w clock width 7 ns f max external feedback 1/(t s + t co )50mhz internal feedback 1/(t sf + t cf )62mhz no feedback 1/(t p ) 71 mhz t aw asynchronous reset width 15 ns t ar asynchronous reset recovery time 15 ns t ap asynchronous reset to registered output reset 15 ns t sp setup time, synchronous preset 8 ns
atf750lvc 6 ac waveforms, input pin clock (1) notes: 1. timing measurement reference is 1.5v. input ac driving levels are 0.0v and 3.0v, unless otherwise specified. ac characteristics, input pin clock symbol parameter -15 units min max t pd input or feedback to non-registered output 15 ns t ea input to output enable 15 ns t er input to output disable 15 ns t cos clock to output 0 10 ns t cfs clock to feedback 0 5.5 ns t ss input setup time 8 ns t sfs feedback setup time 7 ns t hs hold time 0 ns t ps clock period 12 ns t ws clock width 6 ns f maxs external feedback 1/(t ss + t cos )55mhz internal feedback 1/(t sfs + t cfs )80mhz no feedback 1/(t ps ) 83 mhz t aw asynchronous reset width 15 ns t ars asynchronous reset recovery time 15 ns t ap asynchronous reset to registered output reset 15 ns t sps setup time, synchronous preset 11 ns
atf750lvc 7 functional logic diagram atf750lvc, upper half
atf750lvc 8 functional logic diagram atf750lvc, lower half
atf750lvc 9 using the atf750lvc?s many advanced features the atf750lvc ? s advanced flexibility packs more usable gates into 24-pins than any other logic device. the atf750lvcs start with the popular 22v10 architecture, and add several enhanced features: selectable d- and t-type registers each atf750lvc flip-flop can be individually configured as either d- or t-type. using the t-type configuration, jk and sr flip-flops are also easily created. these options allow more efficient product term usage. selectable asynchronous clocks each of the atf750lvc ? s flip-flops may be clocked by its own clock product term or directly from pin 1 (smd lead 2). this removes the constraint that all registers must use the same clock. buried state machines, counters and registers can all coexist in one device while running on separate clocks. individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. a full bank of ten more registers the atf750lvc provides two flip-flops per output logic cell for a total of 20. each register has its own sum term, its own reset term and its own clock term. independent i/o pin and feedback paths each i/o pin on the atf750lvc has a dedicated input path. each of the 20 registers has its own feedback terms into the array as well. this feature, combined with individual product terms for each i/o ? s output enable, facilitates true bi-directional i/o design. synchronous preset and asynchronous reset one synchronous preset line is provided for all 20 registers in the atf750lvc. the appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. appropriate setup and hold times must be met, as shown in the switching waveform diagram. an individual asynchronous reset line is provided for each of the 20 flip-flops. both master and slave halves of the flip- flops are reset when the input signals received force the internal resets high. security fuse usage a single fuse is provided to prevent unauthorized copying of the atf750lvc fuse patterns. once the security fuse is programmed, all fuses will appear programmed during verify. the security fuse should be programmed last, as its effect is immediate.
atf750lvc 10 output source current vs supply voltage (v oh = 2.4v, t a = 25c) -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 3.00 3.25 3.30 3.50 3.60 supply voltage (v) i oh (ma) input current vs input voltage (v cc = 3.3v, t a = 25c) -10.0 -5.0 0.0 5.0 10.0 15.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 input voltage (v) input current (a) supply current vs supply voltage (t a = 25c) 30.0 40.0 50.0 60.0 70.0 3.0 3.3 3.6 supply voltage (v) i cc (ma ) output sink current vs supply voltage (v ol = 0.5v, t a = 25c) 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 3.00 3.25 3.30 3.50 3.60 supply voltage (v) i ol (ma) input clamp current vs input voltage (v cc = 3.3v, t a = 25c) -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 input voltage (v) input current (ma)
atf750lvc 11 output source current vs output voltage (v cc = 3.3v, t a = 25 c) -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 v oh (v) i oh (ma) supply current vs input frequency (v cc = 5.00v, t a = 25 c) 0 40 80 0 5 10 15 20 50 75 100 frequency (mhz) i cc (ma) output source sink current vs output voltage (v cc = 3.3v, t a = 25 c) 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 v ol (v) i ol (ma)
atf750lvc 12 atf750lvc ordering information note: 1. special order only; tssop package requires special thermal management. using ? c ? product for industrial because the v cc conditions are the same for commercial and industrial for 3.3v products, and there is only 15 c difference at the high end of the temperature range, there is very little risk in using ? c ? devices for industrial applications. just de-rate i cc by 15%. t pd (ns) t cos (ns) ext. f maxs (mh z ) ordering code package operation range 15 10 55 atf750lvc-15jc atf750lvc-15pc atf750lvc-15sc atf750lvc-15xc (1) 28j 24p3 24s 24x (1) commercial (0 c to 70 c) atf750lvc-15ji atf750lvc-15pi atf750lvc-15si atf750lvc-15x (1) i 28j 24p3 24s 24x (1) industrial (-40 c to 85 c) package type 28j 28-lead, plastic j-leaded chip carrier (plcc) 24p3 24-lead, 0.300 ? wide, plastic dual inline package (pdip) 24s 24-lead, 0.300 ? wide, plastic gull wing small outline (soic) 24x* 24-lead, 0.173 ? wide, thin shrink small outline (tssop)
atf750lvc 13 packaging information .045(1.14) x 45 pin no. 1 identify .032(.813) .026(.660) .050(1.27) typ .300(7.62) ref sq .045(1.14) x 30 - 45 .022(.559) x 45 max (3x) .012(.305) .008(.203) .021(.533) .013(.330) .430(10.9) .390(9.91) sq .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .456(11.6) .450(11.4) .495(12.6) .485(12.3) sq sq 1.27(32.3) 1.25(31.7) pin 1 .266(6.76) .250(6.35) .090(2.29) max .005(.127) min .070(1.78) .020(.508) .023(.584) .014(.356) .065(1.65) .040(1.02) .325(8.26) .300(7.62) 0 15 ref .400(10.2) max .012(.305) .008(.203) .110(2.79) .090(2.29) .151(3.84) .125(3.18) seating plane .200(5.06) max 1.100(27.94) ref .020(.508) .013(.330) .299(7.60) .291(7.39) .420(10.7) .393(9.98) .105(2.67) .092(2.34) .050(1.27) bsc .616(15.6) .598(15.2) .012(.305) .003(.076) .013(.330) .009(.229) .050(1.27) .015(.381) 8 0 ref pin 1 id *controlling dimension: millimeters 28j, 28-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 ab 24p3, 24-lead, 0.300" wide, plastic dual inline package (pdip) dimensions in inches and (millimeters) jedec standard ms-001 af 24s, 24-lead, 0.300" wide, plastic gull wing small outline (soic) dimensions in inches and (millimeters) 24x, 24-lead, 0.173" wide, thin shrink small outline (tssop) dimensions in millimeters and (inches)*
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